(1) Field of the Invention
The present invention relates to a process for manufacturing a semiconductor device, and more specifically to a method of forming metallization levels with smooth topographies on the semiconductor substrate.
(2) Description of the Prior Art
The trend in the semiconductor industry has been to continually increase device density, while maintaining or reducing the cost of semiconductor devices. The ability to significantly reduce dimensions, of critical device features, has enabled the semiconductor industry to fabricate more circuits on a specific size silicon chip, thus increasing device density. Cost reductions have also been realized by the ability of the industry to obtain smaller, and thus a greater amount of chips, for a specific size silicon wafer. Thus the trend to device micro-minaturazation has been, and is continuing to be, a strong objective of the semiconductor industry. Many semiconductor fabrication disciplines have been a major contributor in the realization of the micro-miniaturazation objective. For example more sophisticated exposure cameras, as well as more sensitive photoresist materials, have allowed the photolithographic discipline to routinely produce sub-micron images in photoresist. Anisotropic, reactive ion etching, (RIE), processes have in turn allowed the transfer of these sub-micron images, in photoresist, to be successfully transferred to underlying materials used in the fabrication of advanced silicon devices. Other semiconductor fabrication disciplines, such as low pressure chemical vapor deposition, (LPCVD), as well as ion implantation, have also been major contributors to the goal of micro-miniaturazation.
In addition to specific fabrication disciplines, aiding the advancement to smaller devices, several key processes have also been major contributors. For example, the ability to use sidewall spacers, by first depositing a material on a specific shape, and then anisotropically removing this material, everywhere except on the sides of the specific shape, has allowed the semiconductor industry to conserve valuable silicon area. Another technique employed to conserve silicon real estate, thus increasing device density, has been the stacked via approach. The stacked via approach is where basically all the vias or contacts, between interconnecting metallizations, or between a metallization and an underlying silicon device element, are created to reside on the same vertical axis. To successfully use the stacked via approach it is essential to create via hole metal fills, as planar, or as smooth as possible. For example if an irregularity, in terms of a metal seam exists in a lower via hole metal fill, this irregularity will be transferred to upper via hole metal fills, usually in a more exaggerated form then had existed for the lower via hole metal fills. This phenomena can result in metal discontinuities, leading to yield losses, or a lack of a sufficient amount of metal in the via hole, leading to possible electromigration failures due to increased current densities.
The attainment of smooth or planar metallizations has been addressed by Deleonibus, et al, in U.S. Pat. No. 4,592,802, and by Aoyama, et al, in U.S. Pat. No. 4,520,041, however these disclosures do not address the practical situation in which an overetch of the metal fill has to be performed, to clear the unwanted material from specific areas. The overetch will result in the metal fill residing well below the top surface if the via hole insulator, making it extremely difficult for subsequent via hole formation and metallizations to proceed in a planar manner. This invention will describe a process, which allows metal overetch, however uses a unique process that will allow subsequent via hole creation and metallization processes to still result in planar togographies.